An Integrated Technology Mapping Environment

This paper describes a flexible and efficient environment for technology mapping featuring a common set of algorithms for both standard cells and LUT-based FPGAs. The algorithms and data structures can be customized for various objectives and constraints, such as delay optimization, area recovery, and power and placement improvement under delay and area constraints. Experimental results show superior results for both standard cells and FPGAs when compared with state-of-the-art mappers.